Hun Namkung

I am a fifth-year PhD student in the ECE Department at Carnegie Mellon University. I am fortunate to be co-advised by Peter Steenkiste and Vyas Sekar. Prior to CMU, I received a BS degree in Computer Science from KAIST. My research interests lie in the intersection of network monitoring and programmable hardware devices. I’m joining Conviva after my Ph.D. graduation.

selected publications (see all)

NSDI

Sketchovsky: Enabling Ensembles of Sketches on Programmable Switches (to appear)

Hun Namkung, Zaoxing Liu, Daehyeok Kim, Vyas Sekar, and Peter Steenkiste

In 20th USENIX Symposium on Networked Systems Design and Implementation (NSDI) 2023
NSDI

SketchLib: Enabling Efficient Sketch-based Monitoring on Programmable Switches

Hun Namkung, Zaoxing Liu, Daehyeok Kim, Vyas Sekar, and Peter Steenkiste

In 19th USENIX Symposium on Networked Systems Design and Implementation (NSDI) 2022

Abs PDF

Sketching algorithms or sketches enable accurate network measurement results with low resource footprints. While emerging programmable switches are an attractive target to get these benefits, current implementations of sketches are either inefficient and/or infeasible on hardware. Our contributions in the paper are: (1) systematically analyzing the resource bottlenecks of existing sketch implementations in hardware; (2) identifying practical and correct-by-construction optimization techniques to tackle the identified bottlenecks; and (3) designing an easy-to-use library called SketchLib to help developers efficiently implement their sketch algorithms in switch hardware to benefit from these resource optimizations. Our evaluation on state-of-the-art sketches demonstrates that SketchLib reduces the hardware resource footprint up to 96% without impacting fidelity.
SOSR

Telemetry Retrieval Inaccuracy in Programmable Switches: Analysis and Recommendations

Hun Namkung, Daehyeok Kim, Zaoxing Liu, Vyas Sekar, and Peter Steenkiste

In Proceedings of the Symposium on SDN Research (SOSR) 2021

Abs PDF

Sketching algorithms or sketches are attractive as telemetry capabilities on programmable hardware switches since they offer rigorous accuracy guarantees and use compact data structures. However, we find that in practice, their actual implementations can have a significant (up to 94\times×) accuracy drop compared to theoretical expectations. We find that the delays incurred by pulling and resetting the data plane state induce accuracy degradation. We design and implement solutions to reduce the delays and show that our solutions can help eliminate almost all the inaccuracy of existing sketch workflows.